Espressif Systems /ESP32-P4 /ASSIST_DEBUG /CORE_1_INTR_RAW

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Interpret as CORE_1_INTR_RAW

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CORE_1_AREA_DRAM0_0_RD_RAW)CORE_1_AREA_DRAM0_0_RD_RAW 0 (CORE_1_AREA_DRAM0_0_WR_RAW)CORE_1_AREA_DRAM0_0_WR_RAW 0 (CORE_1_AREA_DRAM0_1_RD_RAW)CORE_1_AREA_DRAM0_1_RD_RAW 0 (CORE_1_AREA_DRAM0_1_WR_RAW)CORE_1_AREA_DRAM0_1_WR_RAW 0 (CORE_1_AREA_PIF_0_RD_RAW)CORE_1_AREA_PIF_0_RD_RAW 0 (CORE_1_AREA_PIF_0_WR_RAW)CORE_1_AREA_PIF_0_WR_RAW 0 (CORE_1_AREA_PIF_1_RD_RAW)CORE_1_AREA_PIF_1_RD_RAW 0 (CORE_1_AREA_PIF_1_WR_RAW)CORE_1_AREA_PIF_1_WR_RAW 0 (CORE_1_SP_SPILL_MIN_RAW)CORE_1_SP_SPILL_MIN_RAW 0 (CORE_1_SP_SPILL_MAX_RAW)CORE_1_SP_SPILL_MAX_RAW 0 (CORE_1_IRAM0_EXCEPTION_MONITOR_RAW)CORE_1_IRAM0_EXCEPTION_MONITOR_RAW 0 (CORE_1_DRAM0_EXCEPTION_MONITOR_RAW)CORE_1_DRAM0_EXCEPTION_MONITOR_RAW

Description

core1 monitor interrupt status register

Fields

CORE_1_AREA_DRAM0_0_RD_RAW

Core1 dram0 area0 read monitor interrupt status

CORE_1_AREA_DRAM0_0_WR_RAW

Core1 dram0 area0 write monitor interrupt status

CORE_1_AREA_DRAM0_1_RD_RAW

Core1 dram0 area1 read monitor interrupt status

CORE_1_AREA_DRAM0_1_WR_RAW

Core1 dram0 area1 write monitor interrupt status

CORE_1_AREA_PIF_0_RD_RAW

Core1 PIF area0 read monitor interrupt status

CORE_1_AREA_PIF_0_WR_RAW

Core1 PIF area0 write monitor interrupt status

CORE_1_AREA_PIF_1_RD_RAW

Core1 PIF area1 read monitor interrupt status

CORE_1_AREA_PIF_1_WR_RAW

Core1 PIF area1 write monitor interrupt status

CORE_1_SP_SPILL_MIN_RAW

Core1 stackpoint underflow monitor interrupt status

CORE_1_SP_SPILL_MAX_RAW

Core1 stackpoint overflow monitor interrupt status

CORE_1_IRAM0_EXCEPTION_MONITOR_RAW

IBUS busy monitor interrupt status

CORE_1_DRAM0_EXCEPTION_MONITOR_RAW

DBUS busy monitor initerrupt status

Links

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